Systems IP - Staff Formal Verification Engineer

This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the hardworking System IP team!
This is a fast-paced technical role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!
This role is for the Interconnect product team.
The Interconnect team develops the Arm Corelink Interconnect IP family. Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including mobile, IoT, networking infrastructure, automotive etc. The highly scalable IP is optimised for AMBA-compliant SoC connectivity and can be customised for multiple performance points
Responsibilities:
You will specify and develop new hardware verification testbenches for future generation hardware IP. You will improve existing testbenches to increase performance, quality and efficiency. You will also identify areas for improvement in processes and methodologies, then implement those changes to advance our best-practises and state of the art for hardware verification.
The responsibilities of a member of the Verification team are:- Reviewing and assessing proposed design changes from a verification complexity point of view
Ownership of verification environments from investigation all the way to verification closure
Develop, extend, maintain, and improve our SVA Formal testbenches
Develop, extend, maintain and improve our suite of SVA Protocol Checkers for Formal and Simulation use
There will be opportunities for improving our verification methodology, leading and mentoring other members of the team
Close collaboration with other Arm engineering teams leading to high quality IP that works well in a complete system.
Required Skills and Experience:
Experience of architecting, leading and implementing formal verification environments for complex IP/module level designs.
Experience of property-based model-checking or Formal Property verification using SystemVerilog Assertions (SVA) with an industry leading formal tool (e.g. Cadence, Mentor, Synopsys tools).
Ability to quickly understand and apply complex specification details.
Dedicated with a focused approach to problem analysis and solving.
You are able to plan and estimate your own work
'Nice To Have' Skills and Experience:
Team leadership and mentoring experience
Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
Strong communication skills and ability to work well as part of a team.
In return:
You will get to utilise your engineering skills to build support for the technologies and influence millions of devices for years to come. You will be able to drive and bring your ideas to a wider group of our leading experts, build your technical leadership and influencing skills and build towards becoming an established and recognised expert within the existing team.
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